Historically, ECC has been used to correct errors that occur within data patterns provided by semiconductor memories, such as DRAM, SRAM and non-volatile memories. As will be appreciated by those skilled in the art, this involves creating and storing extra bits known as parity bits. The extra data bits required for the ECC (parity bits) are appended to the data or memory. Typically semiconductor memories (both discrete and embedded) have used ECC to correct soft errors caused by radiation.
Typically for every 32 bits of data at least 6 extra bits of data are required. These 6 extra bits of data permit 2 errors to be detected and 1 to be corrected. While the examples in the present application use 32 data bits and 6 parity bits it will be understood that these examples are not intended to limit the scope of the present application and any suitable combination of data bits and parity bits can be used.
A traditional memory with ECC is shown in FIG. 1 and indicated generally by the numeral 10. M bits of data (for example, 32 bits) require N bits of parity data (for example, 6 bits), where M and N are non-zero integer values. The bits of data are stored in a main memory array 12 and the bits of parity data are stored in a parity memory array 14 that is appended to the main memory array 12. In the present example, M data bits DATA[0:m] flow in parallel to and from the I/O circuitry 16 to the main memory array 12 via the ECC logic circuitry 18 and the column decoders 22. For example, the column decoders 22 can be a 2:1, 4:1 or 8:1 multiplexor that connects one of several columns to one I/O. However, it is noted that column decoders may not be necessary if there is a 1:1 correspondence of columns to I/O. From this point forward, descriptions of data being coupled between the I/O circuits and column decoder circuits will be understood to include embodiments having no column decoders such that the I/O circuits are connected directly to the memory array columns or parity memory array columns.
The memory location for reading data from and for writing data to is selected by the row and column decoders 20 and 22 respectively. It is noted that a row generally refers to memory cells connected to a wordline, while a column generally refers to memory cells connected to a bitline. For a write cycle, the I/O circuitry 16 receives M bits of data DO to DM and passes it to the ECC logic circuitry 18. The N parity bits DPO to DPN are generated by the ECC logic circuitry 18 based on the values of the M bits, and the N parity bits and are stored in the parity memory array 14 substantially simultaneously with the storage of the M data bits in the main memory array 12. For a read cycle, the data q0 to qM are selected from the main memory array 12 by the row and column decoders 20, 22, respectively, amplified by the sense amplifiers 24 and presented to the ECC logic circuitry 18. At the same time, the corresponding parity bits QP0 to QPN are read out from the parity array 14. The ECC logic circuitry 18 evaluates whether the data and the parity data is good and corrects errors in the data and/or the parity data if the errors are within the limits for detection/correction. The I/O circuitry 16 then outputs the corrected data Q0 to QM received from ECC logic circuitry 18.
It will be appreciated that control logic 26 controls the row and column decoders 20, 22, respectively, the sense amplifiers 24, the ECC logic circuitry 18 and the I/O circuitry 16 for the read and write cycles in response to commands and address information.
Note that FIG. 1 is shown as a single bank for the purpose of simplicity. Those skilled in the art will realize that multiple banks are possible. Additionally those skilled in the art will realize that pipeline stages can be added at various places in the chip. For example the data can be latched in a pipeline stage before and/or after the ECC block. The sense amplifiers can also be used as pipeline stages.
Reference is now made to FIG. 2 which shows a block diagram of a conceptualization of ECC logic circuitry 18. In the present example, ECC logic circuitry 18 includes an ECC encoder 28, an ECC decoder 30 and a correction block 32. The ECC encoder 28 produces N parity data bits DP[0:n] from M input data bits D[0:m], where m and n are non-zero integer values. Using the 32 bit data example, the ECC encoder 28 and decoder 30 circuits can be implemented with chained XOR gates, where each parity bit is the XOR of 16 bits. Those skilled in the ECC art will understand that the selection of the bits to be combined is based on mathematics of the code. For example, one parity bit is an XOR of bit positions 0, 1, 4, 5, 10, 12, 14, 20, 21, 22, 23, 24, 25, 26, 27 and a logic high input. Four-bit XOR's can be used, thus only requiring 2 stages of 4 bit XOR's. Those skilled in the art will understand that there are several different logic circuit configurations for implementing ECC functionality. These parity data bits and input data bits are sent to the parity memory array 14, and main memory array 12, respectively, via the column decoders 22 during a write cycle. During a read cycle, M bits q[0:m] from the main memory array 12, via the column decoders 22 and sense amplifiers 24, are input to the ECC decoder 30 and the correction block 32. The ECC decoder 30 regenerates the N parity bits, and the N parity bits QP[0:n] from the parity memory array 14 are compared to the regenerated N parity bits within the correction block 32 to determine if the data is correct and which bit or bits are in error and need correction. The data is corrected, if required, and the corrected data Q[0:m] is output from the correction block 32.
Enable signal ECC_EN enables the ECC decoder 30 and the correction block 32. If ECC_EN is active (logic high for example) then the ECC decoder 30 will regenerate parity bits from the memory data q[0:m], and the correction block 32 will correct any errors in the data by using the regenerated parity bits and the parity bits QP[0:n]. If it is inactive, the parity bits are not regenerated by ECC decoder 30 and the correction block 32 outputs only the M bits of data Q[0:m] from the main memory array 12 (shown in FIG. 1).
In the present example, there are separate channels to avoid interference between the semiconductor memory write and read paths through the ECC logic circuitry 18. It will be appreciated that the ECC encoder 28 and the ECC decoder 30 can use the same logic circuitry. It will also be appreciated that rather than having an ECC encoder 28 and separate ECC decoder 30, the ECC input and output paths can share one ECC encoder/decoder to conserve silicon area.
In the physical implementation of the ECC logic circuitry 18, those skilled in the art will understand that the ECC logic circuitry 18 can be distributed in the column direction of the memory array 12, as generally illustrated in FIG. 1. Specific data bits and corresponding parity bits are grouped together in an area of the ECC logic circuitry 18 to facilitate the operations being executed upon them by logic elements. . All the M data bits are routed over wires, as are the N parity bits. However, one or more parity bits will need to be routed from the parity array 14 to a left-most area of ECC logic circuitry 18. Those skilled in the art will understand that long wires results in extra resistive capacitive (RC) delay, thereby limiting ECC performance as the circuitry must wait for the slowest parity bit to arrive before executing ECC operations. Also, increased capacitance results in increased power consumption.
While ECC is used to correct logical errors of data stored in the memory array 12 during normal operation of the memory, memory testing is executed after fabrication to identify physically defective memory cells. Those skilled in the art will understand that anomalies during semiconductor fabrication can cause such defects in the memory array and the logic circuits of the memory. Redundancy in the memory array, including redundant rows and/or columns of memory cells, are available for replacing a regular row or column having a defective memory cell. As shown in FIG. 1, access to the memory array 12 is possible via the I/O circuitry 16 for writing test patterns and for reading out the test patterns. As previously discussed, the ECC decoder 30 and correction block 32 can be disabled such that the parity bits are ignored and only the data bits are output.
Unfortunately, there is no direct I/O access to the parity array allowing a tester to write test patterns to and to read test patterns from, the parity array 14. Therefore, the presence of defective memory cells therein cannot be tested. Furthermore, as fabrication defects can affect the logic elements of the ECC logic circuitry 18, there is no means for testing the logic functionality. It should be well understood that defects in the parity array 14 will result in correct data being inadvertently changed due to a faulty parity bit.
It is therefore desirable to improve the performance and testability of ECC semiconductor memory systems.